[HW] RTL Design Engineer (HW IP)

[딥엑스] [HW] RTL Design Engineer (HW IP)

[모집기간]

09월 08일 ~ 09월 14일

[담당업무]

-Verilog RTL design in a Linux environment

-Simulation model and testbench development

-RTL simulation and verification

-Ability to design RTL IP based on C models and perform IP verification

-Programming languages: Python/Perl, C/C++

[자격요건]

-Experience in ARM-based SoC design

-Experience in designing ARM (AHB, AXI) SoC platforms and peripheral IP

-Experience with FPGA and ASIC design using high-speed interface IPs (PCIe, USB, SATA, DDR/LPDDR, etc.)

-Familiarity with EDA tools such as VCS/NC Sim, Verdi, Design Compiler, PrimeTime, Formality, SpyGlass, etc.

-Experience with design constraint (DC) setup

-Experience in RTL design related to Clock Domain Crossing (CDC)

-Experience with ASIC mass production

-Experience with FPGA prototyping

-Knowledge of artificial neural networks and deep learning

[우대사항]

-Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion

※ The recruitment process may vary depending on the position and application content.

※ Candidates with less than 3 years of experience are required to submit their academic transcripts.

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